TY - GEN
T1 - Fabrication Aspects and Switching Performance of a Self-Sensing 800 V SiC Circuit Breaker Device
AU - Boettcher, Norman
AU - Takamori, Taro
AU - Wada, Keiji
AU - Saito, Wataru
AU - Nishizawa, Shin Ichi
AU - Erlbacher, Tobias
N1 - Funding Information:
The authors would like to thank H. Mitlehner, M. Rommel, A. Hürner, N. Kaminski, A. Würfel, J. Erlekampf and the pi-Fab personnel for fruitful discussions and their efforts towards fabrication of these novel SSCB devices. Moreover, the authors would like to gratefully acknowledge that this work was made possible by sponsorships of Japan Society for the Promotion of Science (JSPS) and German Ministry of Education and Research (BMBF) under grant 03INT501BC ”SiC-DCBreaker”.
Publisher Copyright:
© 2022 IEEE.
PY - 2022
Y1 - 2022
N2 - This work presents the switching performance of a novel solid-state circuit breaker device suitable for DC-applications up to 800 V. These "dual thyristor"devices are manufactured employing a 4H-SiC JFET technology. With respect to scalability, the influence of specific design parameters on the quasi-static output characteristics are discussed along with corresponding fabrication aspects. In order to investigate the switching performance, clamped and unclamped inductive switching (CIS and UIS) experiments at up to 800 V are carried out. In case of CIS, current clearance is achieved within 642 ns after the self-sensed trigger event at 1.75 A. The UIS experiments reveal stable current handling capability during avalanche.
AB - This work presents the switching performance of a novel solid-state circuit breaker device suitable for DC-applications up to 800 V. These "dual thyristor"devices are manufactured employing a 4H-SiC JFET technology. With respect to scalability, the influence of specific design parameters on the quasi-static output characteristics are discussed along with corresponding fabrication aspects. In order to investigate the switching performance, clamped and unclamped inductive switching (CIS and UIS) experiments at up to 800 V are carried out. In case of CIS, current clearance is achieved within 642 ns after the self-sensed trigger event at 1.75 A. The UIS experiments reveal stable current handling capability during avalanche.
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U2 - 10.1109/ISPSD49238.2022.9813628
DO - 10.1109/ISPSD49238.2022.9813628
M3 - Conference contribution
AN - SCOPUS:85134254113
T3 - Proceedings of the International Symposium on Power Semiconductor Devices and ICs
SP - 261
EP - 264
BT - 2022 34th International Symposium on Power Semiconductor Devices and ICs, ISPSD 2022
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 34th IEEE International Symposium on Power Semiconductor Devices and ICs, ISPSD 2022
Y2 - 22 May 2022 through 25 May 2022
ER -