Energy management techniques for SOC design

Hiroto Yasuura, Tohru Ishihara, Masanori Muroyama

Research output: Chapter in Book/Report/Conference proceedingChapter

3 Citations (Scopus)


One of the biggest problems in complicated and high-performance SoC design is management of energy and/or power consumption. In this chapter, we present energy management techniques in system design including HW and SW, SoC architecture and logic design. Dynamic power consumption is the major factor of energy consumption in the current CMOS digital circuits. The dynamic power consumption is affected by supply voltage, load capacitance and switching activity. We present approaches to controlling supply voltage, load capacitance and switching activity dynamically and statically in system architecture and algorithm design levels. We also discuss about the memory architecture for reducing power and energy in HW and SW co-design of SoC. In the future CMOS technology, leakage power consumption becomes dominant, because the threshold voltages are scaled as the transistor size shrinks. We summarize the techniques for reducing leakage power in system architecture design. The contents of the chapter include the following issues; (1) power and energy consumptions in SoC design, (2) tradeoff between energy and performance, (3) tradeoff among energy, QoS (i.e., latency and computational precision), reliability, and flexibility (4) techniques for reducing dynamic power consumption, and (5) leakage power reduction techniques

Original languageEnglish
Title of host publicationEssential Issues in SOC Design
Subtitle of host publicationDesigning Complex Systems-on-Chip
PublisherSpringer Netherlands
Number of pages47
ISBN (Print)1402053517, 9781402053511
Publication statusPublished - 2006
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Engineering(all)


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