Efficient equivalence checker for combinational circuits

Research output: Contribution to journalConference articlepeer-review

59 Citations (Scopus)


This paper describes a novel equivalence checking method for combinational circuits, which utilizes relations among internal signals represented by binary decision diagrams. To verify circuits efficiently, a proper set of internal signals that are independent with each other should be chosen. A heuristic based on analysis of circuit structure is proposed to select such a set of internal signals. The proposed verifier requires only a minute for equivalence checking of all the ISCAS'85 benchmarks on SUN-4/10.

Original languageEnglish
Pages (from-to)629-634
Number of pages6
JournalProceedings - Design Automation Conference
Publication statusPublished - 1996
Externally publishedYes
EventProceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA
Duration: Jun 3 1996Jun 7 1996

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering


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