Dynamically variable line-size cache architecture for merged DRAM/Logic LSIs

Koji Inoue, Koji Kai, Kazuaki Murakami

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called dynamically variable line-size cache (D-VLS caché). The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth on merged DRAM/logic LSIs appropriately. In our evaluation, it is observed that an average memory-access time improvement achieved by a directmapped D-VLS cache is about 20% compared to a conventional direct-mapped cache with fixed 32-byte lines. This performance improvement is better than that of a doubled-size conventional direct-mapped cache*.

Original languageEnglish
Pages (from-to)1048-1057
Number of pages10
JournalIEICE Transactions on Information and Systems
Issue number5
Publication statusPublished - 2000

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence


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