Dynamic tag-check omission: A low power instruction cache architecture exploiting execution footprints

Koji Inoue; Vasily Moshnyaga; Kazuaki Murakami

doi:10.1007/3-540-36612-1_2

Dynamic tag-check omission: A low power instruction cache architecture exploiting execution footprints

Koji Inoue, Vasily Moshnyaga, Kazuaki Murakami

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes an architecture for low-power directmapped instruction caches, called “history-based tag-comparison (HBTC) cache”. The HBTC cache attempts to detect and omit unnecessary tag checks at run time. Execution footprints are recorded in an extended BTB (Branch Target Buffer), and are used to know the cache residence of target instructions before starting cache access. In our simulation, it is observed that our approach can reduce the total count of tag checks by 90 %, resulting in 15 % of cache-energy reduction, with less than 0.5 % performance degradation.

Original language	English
Title of host publication	Power-Aware Computer Systems - 2nd International Workshop, PACS 2002, Revised Papers
Editors	Babak Falsafi, T.N. Vijaykumar
Publisher	Springer Verlag
Pages	18-32
Number of pages	15
ISBN (Print)	3540010289, 9783540010289
DOIs	https://doi.org/10.1007/3-540-36612-1_2
Publication status	Published - 2003
Externally published	Yes
Event	2nd International Workshop on Power-Aware Computer Systems, PACS 2002 - Cambridge, United States Duration: Feb 2 2002 → Feb 2 2002

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	2325
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Other

Other	2nd International Workshop on Power-Aware Computer Systems, PACS 2002
Country/Territory	United States
City	Cambridge
Period	2/2/02 → 2/2/02

All Science Journal Classification (ASJC) codes

Theoretical Computer Science
Computer Science(all)

Access to Document

10.1007/3-540-36612-1_2

Cite this

Inoue, K., Moshnyaga, V., & Murakami, K. (2003). Dynamic tag-check omission: A low power instruction cache architecture exploiting execution footprints. In B. Falsafi, & T. N. Vijaykumar (Eds.), Power-Aware Computer Systems - 2nd International Workshop, PACS 2002, Revised Papers (pp. 18-32). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2325). Springer Verlag. https://doi.org/10.1007/3-540-36612-1_2

Dynamic tag-check omission: A low power instruction cache architecture exploiting execution footprints. / Inoue, Koji; Moshnyaga, Vasily; Murakami, Kazuaki.
Power-Aware Computer Systems - 2nd International Workshop, PACS 2002, Revised Papers. ed. / Babak Falsafi; T.N. Vijaykumar. Springer Verlag, 2003. p. 18-32 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 2325).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Inoue, K, Moshnyaga, V & Murakami, K 2003, Dynamic tag-check omission: A low power instruction cache architecture exploiting execution footprints. in B Falsafi & TN Vijaykumar (eds), Power-Aware Computer Systems - 2nd International Workshop, PACS 2002, Revised Papers. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 2325, Springer Verlag, pp. 18-32, 2nd International Workshop on Power-Aware Computer Systems, PACS 2002, Cambridge, United States, 2/2/02. https://doi.org/10.1007/3-540-36612-1_2

Inoue K, Moshnyaga V, Murakami K. Dynamic tag-check omission: A low power instruction cache architecture exploiting execution footprints. In Falsafi B, Vijaykumar TN, editors, Power-Aware Computer Systems - 2nd International Workshop, PACS 2002, Revised Papers. Springer Verlag. 2003. p. 18-32. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/3-540-36612-1_2

Inoue, Koji ; Moshnyaga, Vasily ; Murakami, Kazuaki. / Dynamic tag-check omission : A low power instruction cache architecture exploiting execution footprints. Power-Aware Computer Systems - 2nd International Workshop, PACS 2002, Revised Papers. editor / Babak Falsafi ; T.N. Vijaykumar. Springer Verlag, 2003. pp. 18-32 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

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Dynamic tag-check omission: A low power instruction cache architecture exploiting execution footprints

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