Digitally controlled ring oscillator using fraction-based series optimization for inductorless reconfigurable all-digital PLL

Ramesh K. Pokharel, Satoshi Hamada, Abhishek Tomar, Shashank Lingala, Prapto Nugroho, Haruichi Kanaya, Keiji Yoshida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Design and implementation of a CMOS multiphase 10b digitally controlled oscillator (DCO) in ring topology that employs fraction-based series to optimize the transistors size, are presented. One of the advantages of using fraction-based series is that it can reduce the power consumption compared to the binary series without any cost of tuning range and phase noise. The proposed DCO, which was implemented on 0.18 μm CMOS technology, features the tuning frequency 600 MHz to 4.27 GHz with power consumption from 10 mW-40 mW. The measured phase noise is -114.7 dBc/Hz (@4 MHz offset) of the carrier frequency 2.75 GHz.

Original languageEnglish
Title of host publication2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers
Pages69-72
Number of pages4
DOIs
Publication statusPublished - 2011
Event2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Phoenix, AR, United States
Duration: Jan 16 2011Jan 19 2011

Publication series

Name2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers

Other

Other2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011
Country/TerritoryUnited States
CityPhoenix, AR
Period1/16/111/19/11

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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