TY - JOUR
T1 - Development of a front-end ASIC for silicon-strip detectors of the J-PARC muon g−2/EDM experiment
AU - J-PARC muon g – 2/EDM collaboration
AU - Sato, Yutaro
AU - Fujita, Yowichi
AU - Hamada, Eitaro
AU - Kishishita, Tetsuichi
AU - Mibe, Tsutomu
AU - Sasaki, Osamu
AU - Shoji, Masayoshi
AU - Suehara, Taikan
AU - Tanaka, Manobu
AU - Tojo, Junji
AU - Tsutsumi, Tuki
AU - Yamanaka, Takashi
AU - Yoshioka, Tamaki
N1 - Funding Information:
This work was supported by the JSPS KAKENHI (Grant No. JP15H05742 ).
Publisher Copyright:
© 2020 Elsevier B.V.
PY - 2020/7/21
Y1 - 2020/7/21
N2 - A front-end application specific integrated circuit (ASIC) with high rate capability and deep memory buffer is needed for the silicon-strip detector for the J-PARC muon g−2/EDM experiment. In this experiment, we reconstruct a positron track from muon decay by the silicon-strip detector and measure the muon anomalous magnetic moment and the electric dipole moment precisely to explore new physics beyond the Standard Model. The front-end ASIC is required to tolerate hit rates of 1.4 MHz per strip, to be stable to the change of hit rate by a factor of 150 from the beginning to the end of the measurement, and to have deep memory for the period of 40μs with 5 ns time resolution. To satisfy the experimental requirements, we designed a prototype ASIC “SliT128B” with the Silterra 180 nm CMOS technology. We report on the design and the performance of the SliT128B.
AB - A front-end application specific integrated circuit (ASIC) with high rate capability and deep memory buffer is needed for the silicon-strip detector for the J-PARC muon g−2/EDM experiment. In this experiment, we reconstruct a positron track from muon decay by the silicon-strip detector and measure the muon anomalous magnetic moment and the electric dipole moment precisely to explore new physics beyond the Standard Model. The front-end ASIC is required to tolerate hit rates of 1.4 MHz per strip, to be stable to the change of hit rate by a factor of 150 from the beginning to the end of the measurement, and to have deep memory for the period of 40μs with 5 ns time resolution. To satisfy the experimental requirements, we designed a prototype ASIC “SliT128B” with the Silterra 180 nm CMOS technology. We report on the design and the performance of the SliT128B.
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U2 - 10.1016/j.nima.2020.164035
DO - 10.1016/j.nima.2020.164035
M3 - Article
AN - SCOPUS:85084282255
SN - 0168-9002
VL - 969
JO - Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
JF - Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment
M1 - 164035
ER -