Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device

Iori Ishikawa; Ikki Nagaoka; Ryota Kashima; Koki Ishida; Kosuke Fukumitsu; Keitaro Oka; Masamitsu Tanaka; Satoshi Kawakami; Teruo Tanimoto; Takatsugu Ono; Akira Fujimaki; Koji Inoue

doi:10.1109/ISCAS48785.2022.9937317

Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device

Iori Ishikawa, Ikki Nagaoka, Ryota Kashima, Koki Ishida, Kosuke Fukumitsu, Keitaro Oka, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Takatsugu Ono, Akira Fujimaki, Koji Inoue

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents the design of an ultra-high-speed, low-power arithmetic unit that supports variable bit-width operations with single flux quantum (SFQ) technology. Because of the high-speed nature of superconductor devices, we can achieve extremely high power-performance efficiency that cannot be achieved by state-of-the-art CMOS devices. To implement the complex function to support the variable bit-width feature, we introduce a novel circuit architecture to maintain the high-speed operation over 50GHz. Our prototype chip design successfully demonstrated 53.5GHz 1.59mW operations.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems, ISCAS 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	3547-3551
Number of pages	5
ISBN (Electronic)	9781665484855
DOIs	https://doi.org/10.1109/ISCAS48785.2022.9937317
Publication status	Published - 2022
Event	2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022 - Austin, United States Duration: May 27 2022 → Jun 1 2022

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2022-May
ISSN (Print)	0271-4310

Conference

Conference	2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022
Country/Territory	United States
City	Austin
Period	5/27/22 → 6/1/22

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1109/ISCAS48785.2022.9937317

Cite this

Ishikawa, I., Nagaoka, I., Kashima, R., Ishida, K., Fukumitsu, K., Oka, K., Tanaka, M., Kawakami, S., Tanimoto, T., Ono, T., Fujimaki, A., & Inoue, K. (2022). Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device. In IEEE International Symposium on Circuits and Systems, ISCAS 2022 (pp. 3547-3551). (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2022-May). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS48785.2022.9937317

Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device. / Ishikawa, Iori; Nagaoka, Ikki; Kashima, Ryota et al.
IEEE International Symposium on Circuits and Systems, ISCAS 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 3547-3551 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2022-May).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ishikawa, I, Nagaoka, I, Kashima, R, Ishida, K, Fukumitsu, K, Oka, K, Tanaka, M, Kawakami, S , Tanimoto, T , Ono, T, Fujimaki, A & Inoue, K 2022, Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device. in IEEE International Symposium on Circuits and Systems, ISCAS 2022. Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2022-May, Institute of Electrical and Electronics Engineers Inc., pp. 3547-3551, 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, United States, 5/27/22. https://doi.org/10.1109/ISCAS48785.2022.9937317

Ishikawa I, Nagaoka I, Kashima R, Ishida K, Fukumitsu K, Oka K et al. Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device. In IEEE International Symposium on Circuits and Systems, ISCAS 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 3547-3551. (Proceedings - IEEE International Symposium on Circuits and Systems). doi: 10.1109/ISCAS48785.2022.9937317

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abstract = "This paper presents the design of an ultra-high-speed, low-power arithmetic unit that supports variable bit-width operations with single flux quantum (SFQ) technology. Because of the high-speed nature of superconductor devices, we can achieve extremely high power-performance efficiency that cannot be achieved by state-of-the-art CMOS devices. To implement the complex function to support the variable bit-width feature, we introduce a novel circuit architecture to maintain the high-speed operation over 50GHz. Our prototype chip design successfully demonstrated 53.5GHz 1.59mW operations.",

author = "Iori Ishikawa and Ikki Nagaoka and Ryota Kashima and Koki Ishida and Kosuke Fukumitsu and Keitaro Oka and Masamitsu Tanaka and Satoshi Kawakami and Teruo Tanimoto and Takatsugu Ono and Akira Fujimaki and Koji Inoue",

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doi = "10.1109/ISCAS48785.2022.9937317",

language = "English",

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AU - Oka, Keitaro

AU - Tanaka, Masamitsu

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AB - This paper presents the design of an ultra-high-speed, low-power arithmetic unit that supports variable bit-width operations with single flux quantum (SFQ) technology. Because of the high-speed nature of superconductor devices, we can achieve extremely high power-performance efficiency that cannot be achieved by state-of-the-art CMOS devices. To implement the complex function to support the variable bit-width feature, we introduce a novel circuit architecture to maintain the high-speed operation over 50GHz. Our prototype chip design successfully demonstrated 53.5GHz 1.59mW operations.

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Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device

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