TY - GEN
T1 - Design of The Ultra-Low-Power Driven VMM Configurations for μW Scale IoT Devices
AU - Takano, Keisuke
AU - Yajima, Takeaki
AU - Kawakami, Satoshi
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - Operating IoT devices by supplying power from an energy harvester and installing AI accelerators in IoT devices are required. Nevertheless, conventionally selected architectures for AI processing require a large amount of power, making it difficult to operate in low-power bands such as IoT devices or even impossible to operate in the first place. Therefore, driving AI accelerators with power that energy harvesters can supply is an issue. However, there has been no past exploration of AI accelerators in the driven of the μW scale. In this paper, we analyze the configuration of Vector Matrix Multiplier, mainly used for AI accelerators, and show the effective configuration for μW scale IoT devices. Using 180nm CMOS to synthesize the four architectures of various sizes, we characterize device performance and analyze energy consumption and circuit area. As a result of the analysis, it shows that the configuration in which all calculations are deployed on the circuit can have the lowest energy consumption. In addition, we found that when there is a limit on circuit area, a configuration in which some calculations are performed in the time domain by lowering the voltage is suitable.
AB - Operating IoT devices by supplying power from an energy harvester and installing AI accelerators in IoT devices are required. Nevertheless, conventionally selected architectures for AI processing require a large amount of power, making it difficult to operate in low-power bands such as IoT devices or even impossible to operate in the first place. Therefore, driving AI accelerators with power that energy harvesters can supply is an issue. However, there has been no past exploration of AI accelerators in the driven of the μW scale. In this paper, we analyze the configuration of Vector Matrix Multiplier, mainly used for AI accelerators, and show the effective configuration for μW scale IoT devices. Using 180nm CMOS to synthesize the four architectures of various sizes, we characterize device performance and analyze energy consumption and circuit area. As a result of the analysis, it shows that the configuration in which all calculations are deployed on the circuit can have the lowest energy consumption. In addition, we found that when there is a limit on circuit area, a configuration in which some calculations are performed in the time domain by lowering the voltage is suitable.
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U2 - 10.1109/MCSoC60832.2023.00018
DO - 10.1109/MCSoC60832.2023.00018
M3 - Conference contribution
AN - SCOPUS:85184661147
T3 - Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023
SP - 65
EP - 72
BT - Proceedings - 2023 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 16th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2023
Y2 - 18 December 2023 through 21 December 2023
ER -