Design of a lifting wavelet processor for one dimensional signal detection

Koichi Kuzume; Koichi Niijima; Shigeru Takano

Design of a lifting wavelet processor for one dimensional signal detection

Koichi Kuzume, Koichi Niijima, Shigeru Takano

Research output: Contribution to journal › Conference article › peer-review

Abstract

This paper presents the realization of a lifting wavelet processor for signal detection on a field programmable gate array (FPGA) device. This processor implements an algorithm for detecting target portions from a signal using an integer type Haar lifting wavelet transform (IHLWT), which we proposed. The VLSI can be designed using a small amount of circuitry, consisting of only 6 multipliers and 9 adders with a pipeline architecture. The VLSI is designed using Hardware Description Language (HDL) and is simulated on the FPGA in practice. The test scenarios covering several kinds of electrocardiogram (ECG) signals are examined thoroughly.

Original language	English
Pages (from-to)	II421-II424
Journal	Midwest Symposium on Circuits and Systems
Volume	2
Publication status	Published - 2004
Event	The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan Duration: Jul 25 2004 → Jul 28 2004

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

@article{db4c20ced52f474e886b826b79f0970c,

title = "Design of a lifting wavelet processor for one dimensional signal detection",

abstract = "This paper presents the realization of a lifting wavelet processor for signal detection on a field programmable gate array (FPGA) device. This processor implements an algorithm for detecting target portions from a signal using an integer type Haar lifting wavelet transform (IHLWT), which we proposed. The VLSI can be designed using a small amount of circuitry, consisting of only 6 multipliers and 9 adders with a pipeline architecture. The VLSI is designed using Hardware Description Language (HDL) and is simulated on the FPGA in practice. The test scenarios covering several kinds of electrocardiogram (ECG) signals are examined thoroughly.",

author = "Koichi Kuzume and Koichi Niijima and Shigeru Takano",

year = "2004",

language = "English",

volume = "2",

pages = "II421--II424",

journal = "Midwest Symposium on Circuits and Systems",

issn = "1548-3746",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings ; Conference date: 25-07-2004 Through 28-07-2004",

}

TY - JOUR

T1 - Design of a lifting wavelet processor for one dimensional signal detection

AU - Kuzume, Koichi

AU - Niijima, Koichi

AU - Takano, Shigeru

PY - 2004

Y1 - 2004

N2 - This paper presents the realization of a lifting wavelet processor for signal detection on a field programmable gate array (FPGA) device. This processor implements an algorithm for detecting target portions from a signal using an integer type Haar lifting wavelet transform (IHLWT), which we proposed. The VLSI can be designed using a small amount of circuitry, consisting of only 6 multipliers and 9 adders with a pipeline architecture. The VLSI is designed using Hardware Description Language (HDL) and is simulated on the FPGA in practice. The test scenarios covering several kinds of electrocardiogram (ECG) signals are examined thoroughly.

AB - This paper presents the realization of a lifting wavelet processor for signal detection on a field programmable gate array (FPGA) device. This processor implements an algorithm for detecting target portions from a signal using an integer type Haar lifting wavelet transform (IHLWT), which we proposed. The VLSI can be designed using a small amount of circuitry, consisting of only 6 multipliers and 9 adders with a pipeline architecture. The VLSI is designed using Hardware Description Language (HDL) and is simulated on the FPGA in practice. The test scenarios covering several kinds of electrocardiogram (ECG) signals are examined thoroughly.

UR - http://www.scopus.com/inward/record.url?scp=11144323218&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=11144323218&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:11144323218

SN - 1548-3746

VL - 2

SP - II421-II424

JO - Midwest Symposium on Circuits and Systems

JF - Midwest Symposium on Circuits and Systems

T2 - The 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings

Y2 - 25 July 2004 through 28 July 2004

ER -

Design of a lifting wavelet processor for one dimensional signal detection

Abstract

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this