TY - GEN
T1 - Design of 5.5GHz LC oscillator using distributed grid of N-well in P-substrate inductor
AU - Rahim, S. A.Enche Ab
AU - Barakat, Adel
AU - Pokharel, Ramesh K.
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2017/1/3
Y1 - 2017/1/3
N2 - This paper presents the design of low noise LC oscillator that employs an enhanced inductor, where a distributed grid of N-well in P-substrate of the inductor was design to improve the quality factor of the inductor, therefore improves the phase noise of the oscillator. The electromagnetic (EM) simulation shows that the total equivalent resistance of an inductor is reduced, which results in a higher quality factor. A 5.5GHz cross-coupled CMOS LC oscillator is designed by using this new inductor. Based on the simulation results, the oscillator shows an improvement of 0.7 dBc/Hz in phase noise at 1MHz offset from the carrier, which results a FOM of 189.
AB - This paper presents the design of low noise LC oscillator that employs an enhanced inductor, where a distributed grid of N-well in P-substrate of the inductor was design to improve the quality factor of the inductor, therefore improves the phase noise of the oscillator. The electromagnetic (EM) simulation shows that the total equivalent resistance of an inductor is reduced, which results in a higher quality factor. A 5.5GHz cross-coupled CMOS LC oscillator is designed by using this new inductor. Based on the simulation results, the oscillator shows an improvement of 0.7 dBc/Hz in phase noise at 1MHz offset from the carrier, which results a FOM of 189.
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U2 - 10.1109/APCCAS.2016.7803949
DO - 10.1109/APCCAS.2016.7803949
M3 - Conference contribution
AN - SCOPUS:85011112350
T3 - 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
SP - 262
EP - 264
BT - 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2016 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2016
Y2 - 25 October 2016 through 28 October 2016
ER -