Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class semi-super junction MOSFET

Syotaro Ono; Wataru Saito; Masakatsu Takashita; Shoichiro Kurushima; Ken'ichi Tokano; Masakazu Yamaguchi

doi:10.1109/ISPSD.2007.4294923

Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class semi-super junction MOSFET

Syotaro Ono, Wataru Saito, Masakatsu Takashita, Shoichiro Kurushima, Ken'ichi Tokano, Masakazu Yamaguchi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

19 Citations (Scopus)

Abstract

We report the experimental results detailed about the n-buffer layer (n-BAL: n-Bottom Assist Layer) of 600V-class Semi-SJ MOSFET, and discuss about the design optimization by comparing the trade-off characteristics between the specific on-resistance (R_onA) and the breakdown voltage (V _B), the avalanche capability and the body diode characteristic for the first time. As design parameters, the thickness ratio T_BAL-ratio and the doping concentration N_BAL were varied in this work. As a result, the V_B=750V, the R_onA=24.6mΩcm², the maximum avalanche current density J_AP=292A/cm² (I _AP=7.6A, E_AS=1.25J/cm²), and softness factor=0.277 were obtained with the structure of T_BAL-ratio=27% and N_BAL=1.0×10¹⁵ cm^-3. The demonstration results showed that NPT (Non Punch Through)-type design (with high T _BAL-ratio and high N_BAL) realized the larger avalanche capability and the softer reverse recovery characteristic compared with PT (Punch Through)-type design.

Original language	English
Title of host publication	Proceedings of 19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07
Pages	25-28
Number of pages	4
DOIs	https://doi.org/10.1109/ISPSD.2007.4294923
Publication status	Published - 2007
Externally published	Yes
Event	19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07 - Jeju Island, Korea, Republic of Duration: May 27 2007 → May 31 2007

Publication series

Name	Proceedings of the International Symposium on Power Semiconductor Devices and ICs
ISSN (Print)	1063-6854

Other

Other	19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07
Country/Territory	Korea, Republic of
City	Jeju Island
Period	5/27/07 → 5/31/07

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/ISPSD.2007.4294923

Cite this

Ono, S., Saito, W., Takashita, M., Kurushima, S., Tokano, K., & Yamaguchi, M. (2007). Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class semi-super junction MOSFET. In Proceedings of 19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07 (pp. 25-28). Article 4294923 (Proceedings of the International Symposium on Power Semiconductor Devices and ICs). https://doi.org/10.1109/ISPSD.2007.4294923

Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class semi-super junction MOSFET. / Ono, Syotaro; Saito, Wataru; Takashita, Masakatsu et al.
Proceedings of 19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07. 2007. p. 25-28 4294923 (Proceedings of the International Symposium on Power Semiconductor Devices and ICs).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ono, S, Saito, W, Takashita, M, Kurushima, S, Tokano, K & Yamaguchi, M 2007, Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class semi-super junction MOSFET. in Proceedings of 19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07., 4294923, Proceedings of the International Symposium on Power Semiconductor Devices and ICs, pp. 25-28, 19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07, Jeju Island, Korea, Republic of, 5/27/07. https://doi.org/10.1109/ISPSD.2007.4294923

Ono S, Saito W, Takashita M, Kurushima S, Tokano K, Yamaguchi M. Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class semi-super junction MOSFET. In Proceedings of 19th International Symposium on Power Semiconductor Devices and ICs, ISPSD'07. 2007. p. 25-28. 4294923. (Proceedings of the International Symposium on Power Semiconductor Devices and ICs). doi: 10.1109/ISPSD.2007.4294923

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abstract = "We report the experimental results detailed about the n-buffer layer (n-BAL: n-Bottom Assist Layer) of 600V-class Semi-SJ MOSFET, and discuss about the design optimization by comparing the trade-off characteristics between the specific on-resistance (RonA) and the breakdown voltage (V B), the avalanche capability and the body diode characteristic for the first time. As design parameters, the thickness ratio TBAL-ratio and the doping concentration NBAL were varied in this work. As a result, the VB=750V, the RonA=24.6mΩcm2, the maximum avalanche current density JAP=292A/cm2 (I AP=7.6A, EAS=1.25J/cm2), and softness factor=0.277 were obtained with the structure of TBAL-ratio=27% and NBAL=1.0×1015 cm-3. The demonstration results showed that NPT (Non Punch Through)-type design (with high T BAL-ratio and high NBAL) realized the larger avalanche capability and the softer reverse recovery characteristic compared with PT (Punch Through)-type design.",

author = "Syotaro Ono and Wataru Saito and Masakatsu Takashita and Shoichiro Kurushima and Ken'ichi Tokano and Masakazu Yamaguchi",

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AB - We report the experimental results detailed about the n-buffer layer (n-BAL: n-Bottom Assist Layer) of 600V-class Semi-SJ MOSFET, and discuss about the design optimization by comparing the trade-off characteristics between the specific on-resistance (RonA) and the breakdown voltage (V B), the avalanche capability and the body diode characteristic for the first time. As design parameters, the thickness ratio TBAL-ratio and the doping concentration NBAL were varied in this work. As a result, the VB=750V, the RonA=24.6mΩcm2, the maximum avalanche current density JAP=292A/cm2 (I AP=7.6A, EAS=1.25J/cm2), and softness factor=0.277 were obtained with the structure of TBAL-ratio=27% and NBAL=1.0×1015 cm-3. The demonstration results showed that NPT (Non Punch Through)-type design (with high T BAL-ratio and high NBAL) realized the larger avalanche capability and the softer reverse recovery characteristic compared with PT (Punch Through)-type design.

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Design concept of n-buffer layer (n-Bottom Assist Layer) for 600V-class semi-super junction MOSFET

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