Design and implementation of low power digital phase-locked loop

M. Saber, Y. Jitsumatsu, M. T.A. Khan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper proposes a low power architecture for second order digital phase-locked loop (DPLL). High power consumption of DPLL results from using a look-up table (LUT) in implementing the numerically controlled oscillator (NCO). A new design for NCO is presented in which no LUT is used. Proposed architecture implemented using field programmable gate array (FPGA) consumed 15.44 mw at 100 MHz clock frequency which means a more than 25% saving in power consumption compared to traditional NCO. Furthermore, proposed method also saves FPGA resources and works at faster clock frequency.

Original languageEnglish
Title of host publicationISITA/ISSSTA 2010 - 2010 International Symposium on Information Theory and Its Applications
Pages928-933
Number of pages6
DOIs
Publication statusPublished - 2010
Event2010 20th International Symposium on Information Theory and Its Applications, ISITA 2010 and the 2010 20th International Symposium on Spread Spectrum Techniques and Applications, ISSSTA 2010 - Taichung, Taiwan, Province of China
Duration: Oct 17 2010Oct 20 2010

Publication series

NameISITA/ISSSTA 2010 - 2010 International Symposium on Information Theory and Its Applications

Other

Other2010 20th International Symposium on Information Theory and Its Applications, ISITA 2010 and the 2010 20th International Symposium on Spread Spectrum Techniques and Applications, ISSSTA 2010
Country/TerritoryTaiwan, Province of China
CityTaichung
Period10/17/1010/20/10

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Information Systems

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