Datarol-II: A fine-grain massively parallel architecture

Tetsuo Kawano, Shigeru Kusakabe, Rin Ichiro Taniguchi, Makoto Amamiya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)


In this paper, we introduce the Datarol-II processor, that can efficiently execute a fine-grain multi-thread program, called Datarol. In order to achieve the efficient multi-thread execution by reducing context switching overhead, we introduce an implicit register load/store mechanism in the execution pipeline. A two-level hierarchical memory system is also introduced in order to reduce memory access latency. The simulation results show that the Datarol-II processor can tolerate remote memory access latencies and execute a fine-grain multi-thread program efficiently.

Original languageEnglish
Title of host publicationPARLE 1994 – Parallel Architectures and Languages Europe - 6th International PARLE Conference, Proceedings
EditorsCostas Halatsis, George Philokyprou, Dimitrios Maritsas, Sergios Theodoridis
PublisherSpringer Verlag
Number of pages4
ISBN (Print)9783540581840
Publication statusPublished - 1994
Event6th International Conference on Parallel Architectures and Languages Europe, PARLE 1994 - Athens, Greece
Duration: Jul 4 1994Jul 8 1994

Publication series

NameLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume817 LNCS
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


Other6th International Conference on Parallel Architectures and Languages Europe, PARLE 1994

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • General Computer Science


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