TY - GEN
T1 - Datarol
T2 - 2nd IEEE Symposium on Parallel and Distributed Processing, SPDP 1990
AU - Amamiya, Makoto
AU - Taniguchi, Rin Ichiro
PY - 1990/1/1
Y1 - 1990/1/1
N2 - Proposes a parallel machine architecture which incorporates an ultra-multiprocessing facility for parallel execution of functional programs. The machine performs parallel executions along a multi-thread control flow called datarol. A datarol program, instead of using a program counter, the instructions to be executed next are explicitly specified in the preceding instructions. The explicitly specified continuation linkage enables the concurrent execution of the instructions of different function instances, as well as the parallel execution of multi-thread control flow within a function instance. Based on a continuation-based execution model, the datarol processor is designed to implement an efficient parallel execution mechanism needed for ultra-multi-processing. First, the datarol concept is discussed in comparison with a dataflow model. Next, the datarol machine architecture and datarol processor design are described. Finally, the evaluation of the datarol architecture is shown.
AB - Proposes a parallel machine architecture which incorporates an ultra-multiprocessing facility for parallel execution of functional programs. The machine performs parallel executions along a multi-thread control flow called datarol. A datarol program, instead of using a program counter, the instructions to be executed next are explicitly specified in the preceding instructions. The explicitly specified continuation linkage enables the concurrent execution of the instructions of different function instances, as well as the parallel execution of multi-thread control flow within a function instance. Based on a continuation-based execution model, the datarol processor is designed to implement an efficient parallel execution mechanism needed for ultra-multi-processing. First, the datarol concept is discussed in comparison with a dataflow model. Next, the datarol machine architecture and datarol processor design are described. Finally, the evaluation of the datarol architecture is shown.
UR - http://www.scopus.com/inward/record.url?scp=0006127561&partnerID=8YFLogxK
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U2 - 10.1109/SPDP.1990.143635
DO - 10.1109/SPDP.1990.143635
M3 - Conference contribution
T3 - Proceedings of the 2nd IEEE Symposium on Parallel and Distributed Processing 1990, SPDP 1990
SP - 726
EP - 735
BT - Proceedings of the 2nd IEEE Symposium on Parallel and Distributed Processing 1990, SPDP 1990
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 9 December 1990 through 13 December 1990
ER -