TY - GEN
T1 - Cu filling characteristics in through-Si via holes by electroless plating with addition of inhibitors
AU - Inoue, F.
AU - Koyanagi, M.
AU - Fukushima, T.
AU - Yamamoto, K.
AU - Tanaka, S.
AU - Wang, Z.
AU - Shingubara, S.
PY - 2009
Y1 - 2009
N2 - In order to realize low resistance through-Si via (TSV) electrodes, Cu electroplating is one of the most promising methods. However, with an increase of the aspect ratio of TSV, a formation of conductive seed layer prior to Cu electroplating is becoming more and more difficult. We propose an alternative approach using the electroless plating of Cu, which utilize displacement plating without catalyst. This method is effective for fabricating a low resistance TSV when combined with a barrier layer which is composed of tungsten (W). We found that an addition of Cl ions drastically suppressed the pinch-off at the entrance of the TSV, and it enabled conformai Cu deposition for high aspect ratio TSVs.
AB - In order to realize low resistance through-Si via (TSV) electrodes, Cu electroplating is one of the most promising methods. However, with an increase of the aspect ratio of TSV, a formation of conductive seed layer prior to Cu electroplating is becoming more and more difficult. We propose an alternative approach using the electroless plating of Cu, which utilize displacement plating without catalyst. This method is effective for fabricating a low resistance TSV when combined with a barrier layer which is composed of tungsten (W). We found that an addition of Cl ions drastically suppressed the pinch-off at the entrance of the TSV, and it enabled conformai Cu deposition for high aspect ratio TSVs.
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U2 - 10.1149/1.3115647
DO - 10.1149/1.3115647
M3 - Conference contribution
AN - SCOPUS:70449635698
SN - 9781615672967
T3 - ECS Transactions
SP - 27
EP - 32
BT - ECS Transactions - Electronics Packaging 3 - 214th ECS Meeting
T2 - Electronics Packaging 3 - 214th ECS Meeting
Y2 - 12 October 2008 through 17 October 2008
ER -