CTX: A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing

H. Furukawa; X. Wen; K. Miyase; Y. Yamato; S. Kajihara; P. Girard; L. T. Wang; M. Tehranipoor

doi:10.1109/ATS.2008.27

CTX: A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing

H. Furukawa, X. Wen, K. Miyase, Y. Yamato, S. Kajihara, P. Girard, L. T. Wang, M. Tehranipoor

Advanced Information and Communication Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

20 Citations (Scopus)

Abstract

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of don't care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.

Original language	English
Title of host publication	Proceedings of the 17th Asian Test Symposium, ATS 2008
Pages	397-402
Number of pages	6
DOIs	https://doi.org/10.1109/ATS.2008.27
Publication status	Published - 2008
Event	17th Asian Test Symposium, ATS 2008 - Sapporo, Japan Duration: Nov 24 2008 → Nov 27 2008

Publication series

Name	Proceedings of the Asian Test Symposium
ISSN (Print)	1081-7735

Other

Other	17th Asian Test Symposium, ATS 2008
Country/Territory	Japan
City	Sapporo
Period	11/24/08 → 11/27/08

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/ATS.2008.27

Cite this

Furukawa, H., Wen, X., Miyase, K., Yamato, Y., Kajihara, S., Girard, P., Wang, L. T., & Tehranipoor, M. (2008). CTX: A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing. In Proceedings of the 17th Asian Test Symposium, ATS 2008 (pp. 397-402). Article 4711623 (Proceedings of the Asian Test Symposium). https://doi.org/10.1109/ATS.2008.27

CTX: A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing. / Furukawa, H.; Wen, X.; Miyase, K. et al.
Proceedings of the 17th Asian Test Symposium, ATS 2008. 2008. p. 397-402 4711623 (Proceedings of the Asian Test Symposium).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Furukawa, H, Wen, X, Miyase, K, Yamato, Y, Kajihara, S, Girard, P, Wang, LT & Tehranipoor, M 2008, CTX: A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing. in Proceedings of the 17th Asian Test Symposium, ATS 2008., 4711623, Proceedings of the Asian Test Symposium, pp. 397-402, 17th Asian Test Symposium, ATS 2008, Sapporo, Japan, 11/24/08. https://doi.org/10.1109/ATS.2008.27

@inproceedings{9ce09f9d5cb54baebe1abc936c5c0c01,

title = "CTX: A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing",

abstract = "At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of don't care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.",

author = "H. Furukawa and X. Wen and K. Miyase and Y. Yamato and S. Kajihara and P. Girard and Wang, {L. T.} and M. Tehranipoor",

year = "2008",

doi = "10.1109/ATS.2008.27",

language = "English",

isbn = "9780769533964",

series = "Proceedings of the Asian Test Symposium",

pages = "397--402",

booktitle = "Proceedings of the 17th Asian Test Symposium, ATS 2008",

note = "17th Asian Test Symposium, ATS 2008 ; Conference date: 24-11-2008 Through 27-11-2008",

}

TY - GEN

T1 - CTX

T2 - 17th Asian Test Symposium, ATS 2008

AU - Furukawa, H.

AU - Wen, X.

AU - Miyase, K.

AU - Yamato, Y.

AU - Kajihara, S.

AU - Girard, P.

AU - Wang, L. T.

AU - Tehranipoor, M.

PY - 2008

Y1 - 2008

N2 - At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of don't care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.

AB - At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs inactive as possible by disabling corresponding clock-control signals of clock-gating circuitry in Stage-1 (Clock-Disabling), and (2) to make as many remaining active FFs as possible to have equal input and output values in Stage-2 (FF-Silencing). CTX effectively reduces launch switching activity, thus yield loss risk, even with a small number of don't care (X) bits as in test compression, without any impact on test data volume, fault coverage, performance, and circuit design.

UR - http://www.scopus.com/inward/record.url?scp=58249096541&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=58249096541&partnerID=8YFLogxK

U2 - 10.1109/ATS.2008.27

DO - 10.1109/ATS.2008.27

M3 - Conference contribution

AN - SCOPUS:58249096541

SN - 9780769533964

T3 - Proceedings of the Asian Test Symposium

SP - 397

EP - 402

BT - Proceedings of the 17th Asian Test Symposium, ATS 2008

Y2 - 24 November 2008 through 27 November 2008

ER -

CTX: A clock-gating-based test relaxation and X-filling scheme for reducing yield loss risk in at-speed scan testing

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