This paper reports that theoretical limits for the superjunction (SJ) and field plate (FP) structures and the optimum application voltage range is discussed with the previous experimental data. The specific on-resistance limit of the SJ structure is as same as that of the FP structure and inverse proportional to the cell aspect ratio γSJ and γFP (= drift thickness/lateral cell pitch). The cell aspect ratio can be easily increased with the breakdown voltage due to the drift thickness. On the other hand, at the low voltage device, the aspect ratio is determined by the lateral cell pitch due to the process technology. At the FP structure, the insulator thickness interferes to increase the aspect ratio. From the viewpoints of the aspect ratio limit and the output capacitance stored energy (Eoss), the SJ structure is effective for high voltage MOSFETs and the FP structure is effective for low voltage ones. The border of the optimum application voltage is 100-200 V.