TY - GEN
T1 - Comparison of theoretical limits between superjunction and field plate structures
AU - Saito, Wataru
PY - 2013
Y1 - 2013
N2 - This paper reports that theoretical limits for the superjunction (SJ) and field plate (FP) structures and the optimum application voltage range is discussed with the previous experimental data. The specific on-resistance limit of the SJ structure is as same as that of the FP structure and inverse proportional to the cell aspect ratio γSJ and γFP (= drift thickness/lateral cell pitch). The cell aspect ratio can be easily increased with the breakdown voltage due to the drift thickness. On the other hand, at the low voltage device, the aspect ratio is determined by the lateral cell pitch due to the process technology. At the FP structure, the insulator thickness interferes to increase the aspect ratio. From the viewpoints of the aspect ratio limit and the output capacitance stored energy (Eoss), the SJ structure is effective for high voltage MOSFETs and the FP structure is effective for low voltage ones. The border of the optimum application voltage is 100-200 V.
AB - This paper reports that theoretical limits for the superjunction (SJ) and field plate (FP) structures and the optimum application voltage range is discussed with the previous experimental data. The specific on-resistance limit of the SJ structure is as same as that of the FP structure and inverse proportional to the cell aspect ratio γSJ and γFP (= drift thickness/lateral cell pitch). The cell aspect ratio can be easily increased with the breakdown voltage due to the drift thickness. On the other hand, at the low voltage device, the aspect ratio is determined by the lateral cell pitch due to the process technology. At the FP structure, the insulator thickness interferes to increase the aspect ratio. From the viewpoints of the aspect ratio limit and the output capacitance stored energy (Eoss), the SJ structure is effective for high voltage MOSFETs and the FP structure is effective for low voltage ones. The border of the optimum application voltage is 100-200 V.
UR - http://www.scopus.com/inward/record.url?scp=84893252732&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84893252732&partnerID=8YFLogxK
U2 - 10.1109/ISPSD.2013.6694461
DO - 10.1109/ISPSD.2013.6694461
M3 - Conference contribution
AN - SCOPUS:84893252732
SN - 9781467351348
T3 - Proceedings of the International Symposium on Power Semiconductor Devices and ICs
SP - 241
EP - 244
BT - 2013 25th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2013
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2013 25th International Symposium on Power Semiconductor Devices and IC's, ISPSD 2013
Y2 - 26 May 2013 through 30 May 2013
ER -