| Translated title of the contribution | C-12-10 A 10.3125-Gb/s Burst-Mode Clock and Data Recovery Circuit with 160-bit Consecutive Identical Digit Tolerance |
|---|---|
| Original language | Japanese |
| Pages (from-to) | 100 |
| Journal | 電子情報通信学会総合大会講演論文集 |
| Volume | 2008 |
| Issue number | 2 |
| Publication status | Published - Mar 5 2008 |
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