TY - GEN
T1 - Approach of a Coding Conventions for Warning and Suggestion in Transpiler for Rust Convert to RTL
AU - Takano, Keisuke
AU - Oda, Tetsuya
AU - Kohata, Masaki
N1 - Publisher Copyright:
© 2020 IEEE.
PY - 2020/10/13
Y1 - 2020/10/13
N2 - The logic circuit design in Field-Programmable Gate Arrays (FPGA) has few method warnings or suggestions based on coding rules. In our previous work, we implement a transpiler for Rust programming language to convert to Register Transfer Level (RTL). The transpiler is designed to encourage learners of hardware description language (HDL) to design highly readable code. Rust has several warnings and suggestions for coding conventions. However, the transpiler does not cover specific errors of the FPGAs. In this work, we implement warnings and suggestions to promote to learn FPGAs.
AB - The logic circuit design in Field-Programmable Gate Arrays (FPGA) has few method warnings or suggestions based on coding rules. In our previous work, we implement a transpiler for Rust programming language to convert to Register Transfer Level (RTL). The transpiler is designed to encourage learners of hardware description language (HDL) to design highly readable code. Rust has several warnings and suggestions for coding conventions. However, the transpiler does not cover specific errors of the FPGAs. In this work, we implement warnings and suggestions to promote to learn FPGAs.
UR - http://www.scopus.com/inward/record.url?scp=85099401433&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85099401433&partnerID=8YFLogxK
U2 - 10.1109/GCCE50665.2020.9292032
DO - 10.1109/GCCE50665.2020.9292032
M3 - Conference contribution
AN - SCOPUS:85099401433
T3 - 2020 IEEE 9th Global Conference on Consumer Electronics, GCCE 2020
SP - 789
EP - 790
BT - 2020 IEEE 9th Global Conference on Consumer Electronics, GCCE 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th IEEE Global Conference on Consumer Electronics, GCCE 2020
Y2 - 13 October 2020 through 16 October 2020
ER -