Approach of a Coding Conventions for Warning and Suggestion in Transpiler for Rust Convert to RTL

Keisuke Takano, Tetsuya Oda, Masaki Kohata

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

The logic circuit design in Field-Programmable Gate Arrays (FPGA) has few method warnings or suggestions based on coding rules. In our previous work, we implement a transpiler for Rust programming language to convert to Register Transfer Level (RTL). The transpiler is designed to encourage learners of hardware description language (HDL) to design highly readable code. Rust has several warnings and suggestions for coding conventions. However, the transpiler does not cover specific errors of the FPGAs. In this work, we implement warnings and suggestions to promote to learn FPGAs.

Original languageEnglish
Title of host publication2020 IEEE 9th Global Conference on Consumer Electronics, GCCE 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages789-790
Number of pages2
ISBN (Electronic)9781728198026
DOIs
Publication statusPublished - Oct 13 2020
Externally publishedYes
Event9th IEEE Global Conference on Consumer Electronics, GCCE 2020 - Kobe, Japan
Duration: Oct 13 2020Oct 16 2020

Publication series

Name2020 IEEE 9th Global Conference on Consumer Electronics, GCCE 2020

Conference

Conference9th IEEE Global Conference on Consumer Electronics, GCCE 2020
Country/TerritoryJapan
CityKobe
Period10/13/2010/16/20

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Electrical and Electronic Engineering
  • Media Technology
  • Instrumentation
  • Computer Networks and Communications
  • Computer Vision and Pattern Recognition

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