TY - GEN
T1 - Adaptive cache-line size management on 3D integrated microprocessors
AU - Ono, Takatsugu
AU - Inoue, Koji
AU - Murakami, Kazuaki
PY - 2009
Y1 - 2009
N2 - The memory bandwidth can dramatically be improved by means of stacking the main memory (DRAM) on processor cores and connecting them by wide on-chip buses composed of through silicon vias (TSVs). The 3D stacking makes it possible to reduce the cache miss penalty because large amount of data can be transferred from the main memory to the cache at a time. If a large cache line size is employed, we can expect the effect of prefetching. However, it might worsen the system performance if programs do not have enough spatial localities of memory references. To solve this problem, we introduce software-controllable variable line-size cache scheme. In this paper, we apply it to an L1 data cache with 3D stacked DRAM organization. In our evaluation, it is observed that our approach reduces the L1 data cache and stacked DRAM energy consumption up to 75%, compared to a conventional cache.
AB - The memory bandwidth can dramatically be improved by means of stacking the main memory (DRAM) on processor cores and connecting them by wide on-chip buses composed of through silicon vias (TSVs). The 3D stacking makes it possible to reduce the cache miss penalty because large amount of data can be transferred from the main memory to the cache at a time. If a large cache line size is employed, we can expect the effect of prefetching. However, it might worsen the system performance if programs do not have enough spatial localities of memory references. To solve this problem, we introduce software-controllable variable line-size cache scheme. In this paper, we apply it to an L1 data cache with 3D stacked DRAM organization. In our evaluation, it is observed that our approach reduces the L1 data cache and stacked DRAM energy consumption up to 75%, compared to a conventional cache.
UR - http://www.scopus.com/inward/record.url?scp=77951428838&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77951428838&partnerID=8YFLogxK
U2 - 10.1109/SOCDC.2009.5423920
DO - 10.1109/SOCDC.2009.5423920
M3 - Conference contribution
AN - SCOPUS:77951428838
SN - 9781424450343
T3 - 2009 International SoC Design Conference, ISOCC 2009
SP - 472
EP - 475
BT - 2009 International SoC Design Conference, ISOCC 2009
T2 - 2009 International SoC Design Conference, ISOCC 2009
Y2 - 22 November 2009 through 24 November 2009
ER -
