Abstract
This paper presents the design and implementation of a quadrature voltage-controlled ring oscillator with the improved figure of merit (FOM) using the four single-ended inverter topology. Furthermore, a new architecture to prevent the latch-up in even number of stages composed of single-ended ring inverters is proposed. The design is implemented in 0.18µm CMOS technology and the measurement results show a FOM of -163.8dBc/Hz with the phase noise of -125.8dBc/Hz at 4MHz offset from the carrier frequency of 3.4GHz. It exhibits a frequency tuning range from 1.23GHz to 4.17GHz with coarse and fine frequency tuning sensitivity of 1.08MHz/mV and 120kHz/mV, respectively.
Original language | English |
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Pages (from-to) | 1524-1532 |
Number of pages | 9 |
Journal | IEICE Transactions on Electronics |
Volume | 94 |
Issue number | 10 |
DOIs | |
Publication status | Published - Oct 1 2011 |