A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack

Farhad Mehdipour; Krishna Chaitanya Nunna; Lovic Gauthier; Koji Inoue; Kazuaki Murakami

doi:10.1109/3DIC.2012.6263034

A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack

Farhad Mehdipour, Krishna Chaitanya Nunna, Lovic Gauthier, Koji Inoue, Kazuaki Murakami

Department of I&E Visionaries

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Citation (Scopus)

Abstract

Thermal management is one of the main concerns in three-dimensional integration due to difficulty of dissipating heat through the stack of the integrated circuit. In a 3D stack involving a data-path accelerator, a base processor and memory components, peak temperature reduction is targeted in this paper. A mapping algorithm has been devised in order to distribute operations of data flow graphs evenly over the processing elements of the target accelerator in two steps involving thermal-aware partitioning of input data flow graphs, and thermal-aware mapping of the partitions onto the processing elements. The efficiency of the proposed technique in reducing peak temperature is demonstrated throughout the experiments.

Original language	English
Title of host publication	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs	https://doi.org/10.1109/3DIC.2012.6263034
Publication status	Published - 2011
Event	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan Duration: Jan 31 2012 → Feb 2 2012

Publication series

Name	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Other

Other	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Country/Territory	Japan
City	Osaka
Period	1/31/12 → 2/2/12

All Science Journal Classification (ASJC) codes

Control and Systems Engineering

Access to Document

10.1109/3DIC.2012.6263034

Cite this

Mehdipour, F., Nunna, K. C., Gauthier, L., Inoue, K., & Murakami, K. (2011). A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack. In 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 Article 6263034 (2011 IEEE International 3D Systems Integration Conference, 3DIC 2011). https://doi.org/10.1109/3DIC.2012.6263034

A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack. / Mehdipour, Farhad; Nunna, Krishna Chaitanya; Gauthier, Lovic et al.
2011 IEEE International 3D Systems Integration Conference, 3DIC 2011. 2011. 6263034 (2011 IEEE International 3D Systems Integration Conference, 3DIC 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Mehdipour, F, Nunna, KC, Gauthier, L, Inoue, K & Murakami, K 2011, A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack. in 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011., 6263034, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, Osaka, Japan, 1/31/12. https://doi.org/10.1109/3DIC.2012.6263034

@inproceedings{365bbf8400fe42aba1bce2effea6eac1,

title = "A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack",

abstract = "Thermal management is one of the main concerns in three-dimensional integration due to difficulty of dissipating heat through the stack of the integrated circuit. In a 3D stack involving a data-path accelerator, a base processor and memory components, peak temperature reduction is targeted in this paper. A mapping algorithm has been devised in order to distribute operations of data flow graphs evenly over the processing elements of the target accelerator in two steps involving thermal-aware partitioning of input data flow graphs, and thermal-aware mapping of the partitions onto the processing elements. The efficiency of the proposed technique in reducing peak temperature is demonstrated throughout the experiments.",

author = "Farhad Mehdipour and Nunna, {Krishna Chaitanya} and Lovic Gauthier and Koji Inoue and Kazuaki Murakami",

year = "2011",

doi = "10.1109/3DIC.2012.6263034",

language = "English",

isbn = "9781467321891",

series = "2011 IEEE International 3D Systems Integration Conference, 3DIC 2011",

booktitle = "2011 IEEE International 3D Systems Integration Conference, 3DIC 2011",

}

TY - GEN

T1 - A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack

AU - Mehdipour, Farhad

AU - Nunna, Krishna Chaitanya

AU - Gauthier, Lovic

AU - Inoue, Koji

AU - Murakami, Kazuaki

PY - 2011

Y1 - 2011

N2 - Thermal management is one of the main concerns in three-dimensional integration due to difficulty of dissipating heat through the stack of the integrated circuit. In a 3D stack involving a data-path accelerator, a base processor and memory components, peak temperature reduction is targeted in this paper. A mapping algorithm has been devised in order to distribute operations of data flow graphs evenly over the processing elements of the target accelerator in two steps involving thermal-aware partitioning of input data flow graphs, and thermal-aware mapping of the partitions onto the processing elements. The efficiency of the proposed technique in reducing peak temperature is demonstrated throughout the experiments.

AB - Thermal management is one of the main concerns in three-dimensional integration due to difficulty of dissipating heat through the stack of the integrated circuit. In a 3D stack involving a data-path accelerator, a base processor and memory components, peak temperature reduction is targeted in this paper. A mapping algorithm has been devised in order to distribute operations of data flow graphs evenly over the processing elements of the target accelerator in two steps involving thermal-aware partitioning of input data flow graphs, and thermal-aware mapping of the partitions onto the processing elements. The efficiency of the proposed technique in reducing peak temperature is demonstrated throughout the experiments.

UR - http://www.scopus.com/inward/record.url?scp=84866846587&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866846587&partnerID=8YFLogxK

U2 - 10.1109/3DIC.2012.6263034

DO - 10.1109/3DIC.2012.6263034

M3 - Conference contribution

AN - SCOPUS:84866846587

SN - 9781467321891

T3 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

BT - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

T2 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Y2 - 31 January 2012 through 2 February 2012

ER -

A thermal-aware mapping algorithm for reducing peak temperature of an accelerator deployed in a 3D stack

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