A test pattern compaction method using SAT-based fault grouping

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This paper presents a test pattern compaction algorithm applicable for large scale circuits. The proposed methods formalizes the test pattern compaction problem as a problem finding minimum set of compatible fault groups. Also, an efficient algorithm checking compatibility of fault group is proposed. The experimental results show that the proposed algorithm achieves similar or better results against a couple of existing methods, especially for middle circuits.

Original languageEnglish
Pages (from-to)2302-2309
Number of pages8
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number12
Publication statusPublished - Dec 2016

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics


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