TY - GEN
T1 - A Survey of Formal Techniques for Hardware/Software Co-verification
AU - Liu, Kun
AU - Kong, Weiqiang
AU - Hou, Gang
AU - Fukuda, Akira
N1 - Funding Information:
ACKNOWLEDGMENT This research is supported by National Natural Science Foundation of China (Grant No. 6157209761402073) and by the Fundamental Research Funds for the Central Universities (Grant No. DUT18JC08). The work of Akira Fukuda is partially supported by JSPS KAKENHI Grant No. 15H05708.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/7/2
Y1 - 2018/7/2
N2 - A growing trend for today's intelligent automotive industry is co-design of hardware alongside embedded, low-level software that closely interacts with it. Formal techniques have emerged as alternative ways to ensure the quality and correctness of embedded systems, overcoming some of the deficiencies of traditional validation techniques such as simulation and testing. Tighter integration of hardware and software components makes a strong case for the need of formal co-verification tools. In order to provide insight into the scope of currently available formal techniques, we survey a variety of frameworks and techniques proposed in the literature and applied to actual designs. There are two main aspects about the application of formal co-verification techniques: unified property specification and co-verification framework used to specify desired properties.
AB - A growing trend for today's intelligent automotive industry is co-design of hardware alongside embedded, low-level software that closely interacts with it. Formal techniques have emerged as alternative ways to ensure the quality and correctness of embedded systems, overcoming some of the deficiencies of traditional validation techniques such as simulation and testing. Tighter integration of hardware and software components makes a strong case for the need of formal co-verification tools. In order to provide insight into the scope of currently available formal techniques, we survey a variety of frameworks and techniques proposed in the literature and applied to actual designs. There are two main aspects about the application of formal co-verification techniques: unified property specification and co-verification framework used to specify desired properties.
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U2 - 10.1109/IIAI-AAI.2018.00033
DO - 10.1109/IIAI-AAI.2018.00033
M3 - Conference contribution
AN - SCOPUS:85065213258
T3 - Proceedings - 2018 7th International Congress on Advanced Applied Informatics, IIAI-AAI 2018
SP - 125
EP - 128
BT - Proceedings - 2018 7th International Congress on Advanced Applied Informatics, IIAI-AAI 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th International Congress on Advanced Applied Informatics, IIAI-AAI 2018
Y2 - 8 July 2018 through 13 July 2018
ER -