TY - GEN
T1 - A small die area and high linearity 10-bit capacitive three-level DAC
AU - Oshiro, Keigo
AU - Kanemoto, Daisuke
AU - Kanaya, Haruichi
AU - Pokharel, Ramesh
AU - Yoshida, Keiji
PY - 2012
Y1 - 2012
N2 - A 10-bit capacitive three-level digital-to-analog converter (TLDAC) is provided to reduce differential non-linearity (DNL) and integral non-linearity (INL) caused by capacitive mismatch. The simulation results of binary-weighted TLDAC show 50 % reduction in DNL and INL compared to conventional binary-weighted DAC. Furthermore an additional reference voltage source has been reduced due to the advantages of differential circuit. The proposed 10-bit differential TLDAC was implemented in 0.18 μm CMOS process and its total area is 0.081 mm2.
AB - A 10-bit capacitive three-level digital-to-analog converter (TLDAC) is provided to reduce differential non-linearity (DNL) and integral non-linearity (INL) caused by capacitive mismatch. The simulation results of binary-weighted TLDAC show 50 % reduction in DNL and INL compared to conventional binary-weighted DAC. Furthermore an additional reference voltage source has been reduced due to the advantages of differential circuit. The proposed 10-bit differential TLDAC was implemented in 0.18 μm CMOS process and its total area is 0.081 mm2.
UR - http://www.scopus.com/inward/record.url?scp=84874174295&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84874174295&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2012.6418997
DO - 10.1109/APCCAS.2012.6418997
M3 - Conference contribution
AN - SCOPUS:84874174295
SN - 9781457717291
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 164
EP - 167
BT - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
T2 - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Y2 - 2 December 2012 through 5 December 2012
ER -