A single cycle accessible two-level cache architecture for the energy consumption of embedded systems

Employing a small L0-cache between an MPU core an L1-cache is one of the most promising approaches for reducing energy consumption of memory subsystems. Since the -cache is small, if there is a hit, the energy consumption will be. On the other hand, if there is a miss, one extra cycle is to access the L1-cache. This leads to a degradation of processor performance. For resolving this problem, a Single accessible Two-level Cache (STC) architecture is proposed this paper. This architecture makes it possible to access to both L0 and the L1 caches from an MPU core in a cycle. Experiments several benchmark programs demonstrate that STC architecture reduces the energy consumption of memory by 13% without any performance degradation compared the best results obtained by previous approaches.