A self-biasing class-E power amplifier for 5-GHz constant envelope modulation system

Yuki Yamashita; Daisuke Kanemoto; Haruichi Kanaya; Ramesh K. Pokharel; Keiji Yoshida

doi:10.1587/elex.10.20130174

A self-biasing class-E power amplifier for 5-GHz constant envelope modulation system

Yuki Yamashita, Daisuke Kanemoto, Haruichi Kanaya, Ramesh K. Pokharel, Keiji Yoshida

Research output: Contribution to journal › Article › peer-review

Abstract

This paper describes the design of 5-GHz fully integrated self-biasing power amplifier (PA) for wireless transmitter applications in a 0.18-µm CMOS technology. The proposed class-E PA employs the cascode topology with a self-biasing technique to reduce device stress. Three cascaded class-D driver amplifiers are used to actualize the sharp switching at the class-E power stage. All device components are integrated on chip and the chip area is 1.0×1.3mm<sup>2</sup>. The measurement results indicate that the PA delivers 16.4dBm output power and 35.4% power-added efficiency with 2.3V power supply voltage into a 50Ω load.

Original language	English
Pages (from-to)	20130174-20130174
Number of pages	1
Journal	IEICE Electronics Express
Volume	10
Issue number	8
DOIs	https://doi.org/10.1587/elex.10.20130174
Publication status	Published - 2013

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https://doi.org/10.1587/elex.10.20130174

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title = "A self-biasing class-E power amplifier for 5-GHz constant envelope modulation system",

abstract = "This paper describes the design of 5-GHz fully integrated self-biasing power amplifier (PA) for wireless transmitter applications in a 0.18-µm CMOS technology. The proposed class-E PA employs the cascode topology with a self-biasing technique to reduce device stress. Three cascaded class-D driver amplifiers are used to actualize the sharp switching at the class-E power stage. All device components are integrated on chip and the chip area is 1.0×1.3mm2. The measurement results indicate that the PA delivers 16.4dBm output power and 35.4% power-added efficiency with 2.3V power supply voltage into a 50Ω load.",

author = "Yuki Yamashita and Daisuke Kanemoto and Haruichi Kanaya and Pokharel, {Ramesh K.} and Keiji Yoshida",

year = "2013",

doi = "10.1587/elex.10.20130174",

language = "English",

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AU - Yamashita, Yuki

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AU - Kanaya, Haruichi

AU - Pokharel, Ramesh K.

AU - Yoshida, Keiji

PY - 2013

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AB - This paper describes the design of 5-GHz fully integrated self-biasing power amplifier (PA) for wireless transmitter applications in a 0.18-µm CMOS technology. The proposed class-E PA employs the cascode topology with a self-biasing technique to reduce device stress. Three cascaded class-D driver amplifiers are used to actualize the sharp switching at the class-E power stage. All device components are integrated on chip and the chip area is 1.0×1.3mm2. The measurement results indicate that the PA delivers 16.4dBm output power and 35.4% power-added efficiency with 2.3V power supply voltage into a 50Ω load.

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DO - 10.1587/elex.10.20130174

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JO - IEICE Electronics Express

JF - IEICE Electronics Express

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ER -

A self-biasing class-E power amplifier for 5-GHz constant envelope modulation system

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