A selective replacement method for timing-error-predicting flip-flops

The aggressive technology scaling brings us new challenges, such as parameter variations, soft errors, and device wearout. They increase unreliability of transistors and thus will become a serious problem in SoC designs. To attack these problems, spatial redundancy is commonly utilized. Based on the spatial redundancy, a lot of dual-sensing flip-flops (FFs) are proposed. These FFs require additional circuits consisting of a redundant FF and a comparator. Thus, they suffer large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method. We focus our attention on a timing-error-predicting FF, named canary FF and evaluate the selective replacement method. We apply it to two commercial processors, Toshiba's MeP and Renesas Electronics's M32R. In the case of MeP, the area overhead is reduced from 55% to 11%.