A replacement strategy for canary Flip-Flops

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

The deep submicron semiconductor technologies increase parameter variations. The increase in parameter variations requires excessive design margin that has serious impact on performance and power consumption. In order to eliminate the excessive design margin, we are investigating canary Flip-Flop (FF). Canary FF requires additional circuits consisting of an FF and a comparator. Thus, it suffers large area overhead. In order to reduce the area overhead, this paper proposes a selective replacement method for canary FF and evaluates it. In the case of Renesas's M32R processor, the area overhead of 2% is achieved.

Original languageEnglish
Title of host publicationProceedings - 16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010
Pages227-228
Number of pages2
DOIs
Publication statusPublished - 2010
Event16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010 - Tokyo, Japan
Duration: Dec 13 2010Dec 15 2010

Publication series

NameProceedings - 16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010

Other

Other16th IEEE Pacific Rim International Symposium on Dependable Computing, PRDC 2010
Country/TerritoryJapan
CityTokyo
Period12/13/1012/15/10

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics

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