A pipelined microprocessor for logic programming languages

Hiroshi Nakashima, Yasutaka Takeda, Katsuto Nakajima, Hideki Andou, Kiyohiro Furutani

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    4 Citations (Scopus)

    Abstract

    The architecture of a pipelined microprocessor for logic programming languages is presented. The microprocessor, called PU (processing unit), is also used as a key component of AI workstations. PU has the capability to execute two different logic programming languages, KL1 for PIM/m and ESP for the AI workstation. The microprocessor has very high performance, 833 KLIPS in KL1 append and 1282 KLIPS in ESP, owing to the pipelined data typing and dereference. For efficient implementation of both languages, data typing and dereference are important. For these operations, PU has mechanisms to manipulate tagged data. The hardware architecture of PU is described, focusing on its data typing and dereference mechanisms.

    Original languageEnglish
    Title of host publicationProceedings - IEEE International Conference on Computer Design
    Subtitle of host publicationVLSI in Computers and Processors
    PublisherPubl by IEEE
    Pages355-359
    Number of pages5
    ISBN (Print)O81862079X
    Publication statusPublished - Sept 1990
    EventProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90 - Cambridge, MA, USA
    Duration: Sept 17 1990Sept 19 1990

    Publication series

    NameProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

    Other

    OtherProceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors - ICCD '90
    CityCambridge, MA, USA
    Period9/17/909/19/90

    All Science Journal Classification (ASJC) codes

    • Hardware and Architecture
    • Electrical and Electronic Engineering

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