A novel high-precision DAC utilizing tribonacci series

Kazuya Hokazono; Daisuke Kanemoto; Haruichi Kanaya; Ramesh Pokharel; Keiji Yoshida

doi:10.1587/elex.9.515

A novel high-precision DAC utilizing tribonacci series

Kazuya Hokazono, Daisuke Kanemoto, Haruichi Kanaya, Ramesh Pokharel, Keiji Yoshida

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

A novel Digital-to-Analog Converter (DAC) utilizing Tribonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The proposed DAC has the features that the DNL can be superior to that of a binary DAC and the INL can be superior to that of a unary DAC. In the proposed DAC on a 0.18 μm CMOS process, the number of logic gates can be achieved an around 52% reduction compared to that of the unary DAC.

Original language	English
Pages (from-to)	515-521
Number of pages	7
Journal	IEICE Electronics Express
Volume	9
Issue number	6
DOIs	https://doi.org/10.1587/elex.9.515
Publication status	Published - Mar 25 2012

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Electrical and Electronic Engineering

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AU - Kanaya, Haruichi

AU - Pokharel, Ramesh

AU - Yoshida, Keiji

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AB - A novel Digital-to-Analog Converter (DAC) utilizing Tribonacci Series is presented in this paper. The ratios of successive weights are smaller than those of binary DAC and larger than those of unary DAC. The proposed DAC has the features that the DNL can be superior to that of a binary DAC and the INL can be superior to that of a unary DAC. In the proposed DAC on a 0.18 μm CMOS process, the number of logic gates can be achieved an around 52% reduction compared to that of the unary DAC.

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A novel high-precision DAC utilizing tribonacci series

Abstract

All Science Journal Classification (ASJC) codes

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