A novel and practical control scheme for inter-clock at-speed testing

Hiroshi Furukawa, Xiaoqing Wen, Laung Terng Wang, Boryau Sheu, Zhigang Jiang, Shianling Wu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

17 Citations (Scopus)


The quality of at-speed testing is being severely challenged by the problem that an inter-clock logic block existing between two synchronous clocks is not efficiently tested or totally ignored due to complex test control. This paper addresses the problem with a novel inter-clock at-speed test control scheme, featuring a compact and robust on-chip inter-clock enable generator design. The new scheme can generate inter-clock at-speed test clocks from PLLs, and is feasible for both ATE-based scan testing and logic BIST. Successful applications to industrial circuits have proven its effectiveness in improving the quality of at-speed testing.

Original languageEnglish
Title of host publication2006 IEEE International Test Conference, ITC
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)1424402921, 9781424402922
Publication statusPublished - Jan 1 2006
Event2006 IEEE International Test Conference, ITC - Santa Clara, CA, United States
Duration: Oct 22 2006Oct 27 2006

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539


Other2006 IEEE International Test Conference, ITC
Country/TerritoryUnited States
CitySanta Clara, CA

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics


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