TY - GEN
T1 - A new VLSI algorithm for high throughput image filtering
AU - Islam, Farhad Fuad
AU - Yasuura, Hiroto
AU - Tamaru, Keikichi
N1 - Publisher Copyright:
© 1992 IEEE.
PY - 1992
Y1 - 1992
N2 - A new algorithm for multiplication-accumulation process, suitable for high throughput image filtering operation, is proposed. This algorithm exploits a-priori knowledge of filter masks. Note that, in the past, such a-priori knowledge have often been utilized for avoiding multiplications of pixels by zero elements present in a filter mask. However, the algorithm proposed in this work exploits a-priori knowledge of not only the zero elements of a filter mask, but also that of the zero-bit positions in each of its non-zero elements as well. This results in a throughput [=l/(Time interval between two output filtered pixels)] which is higher than other usual algorithms for multiplication accumulation used in image filtering. The VLSI architecture realizing the new algorithm is also proposed. Experimental result is provided considering a 5 × 5 filter mask. The result indicates 49% reduction in computation time while filtering a 512×512 pixel picture frame. This reduction is achieved without any additional requirement of VLSI layout area for logic gates.
AB - A new algorithm for multiplication-accumulation process, suitable for high throughput image filtering operation, is proposed. This algorithm exploits a-priori knowledge of filter masks. Note that, in the past, such a-priori knowledge have often been utilized for avoiding multiplications of pixels by zero elements present in a filter mask. However, the algorithm proposed in this work exploits a-priori knowledge of not only the zero elements of a filter mask, but also that of the zero-bit positions in each of its non-zero elements as well. This results in a throughput [=l/(Time interval between two output filtered pixels)] which is higher than other usual algorithms for multiplication accumulation used in image filtering. The VLSI architecture realizing the new algorithm is also proposed. Experimental result is provided considering a 5 × 5 filter mask. The result indicates 49% reduction in computation time while filtering a 512×512 pixel picture frame. This reduction is achieved without any additional requirement of VLSI layout area for logic gates.
UR - http://www.scopus.com/inward/record.url?scp=85067257375&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85067257375&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.1992.230523
DO - 10.1109/ISCAS.1992.230523
M3 - Conference contribution
AN - SCOPUS:85067257375
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2441
EP - 2444
BT - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992
Y2 - 10 May 1992 through 13 May 1992
ER -