TY - JOUR
T1 - A New Single-Phase Five-Level Inverter Topology for Single and Multiple Switches Fault Tolerance
AU - Aly, Mokhtar
AU - Ahmed, Emad M.
AU - Shoyama, Masahito
N1 - Publisher Copyright:
© 1986-2012 IEEE.
PY - 2018/11
Y1 - 2018/11
N2 - Reliability of power inverters is of dominant importance in various applications, including industrial, military, aerospace, and commercial applications. Therefore, developing fault tolerant (FT) power inverters is extremely needed from the viewpoints of system availability and avoiding harmful consequences. Tolerating various types of faults, preserving full output ratings after the fault, and being cost-effective represent the main challenges for most of existing FT solutions. In this paper, a new FT single-phase five-level inverter topology is proposed. The proposed topology can effectively tolerate both of single or multiple switches faults whether they are of open-or short-circuit fault types. Moreover, the proposed topology does not deteriorate system efficiency in postfault operation compared to the previously developed FT solutions. Evaluation of the effectiveness and robustness of the proposed topology is verified in both of simulation and experimental environments. Different case studies are investigated in order to cover various types and locations of switches' faults. Moreover, comprehensive comparisons are provided to validate the superiority of the proposed topology over the previously addressed techniques.
AB - Reliability of power inverters is of dominant importance in various applications, including industrial, military, aerospace, and commercial applications. Therefore, developing fault tolerant (FT) power inverters is extremely needed from the viewpoints of system availability and avoiding harmful consequences. Tolerating various types of faults, preserving full output ratings after the fault, and being cost-effective represent the main challenges for most of existing FT solutions. In this paper, a new FT single-phase five-level inverter topology is proposed. The proposed topology can effectively tolerate both of single or multiple switches faults whether they are of open-or short-circuit fault types. Moreover, the proposed topology does not deteriorate system efficiency in postfault operation compared to the previously developed FT solutions. Evaluation of the effectiveness and robustness of the proposed topology is verified in both of simulation and experimental environments. Different case studies are investigated in order to cover various types and locations of switches' faults. Moreover, comprehensive comparisons are provided to validate the superiority of the proposed topology over the previously addressed techniques.
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U2 - 10.1109/TPEL.2018.2792146
DO - 10.1109/TPEL.2018.2792146
M3 - Article
AN - SCOPUS:85041201363
SN - 0885-8993
VL - 33
SP - 9198
EP - 9208
JO - IEEE Transactions on Power Electronics
JF - IEEE Transactions on Power Electronics
IS - 11
M1 - 8253839
ER -