TY - JOUR
T1 - A low-temperature fabricated gate-stack structure for Ge-based MOSFET with ferromagnetic epitaxial Heusler-alloy/Ge electrodes
AU - Fujita, Yuichi
AU - Yamada, Michihiro
AU - Nagatomi, Yuta
AU - Yamamoto, Keisuke
AU - Yamada, Shinya
AU - Sawano, Kentarou
AU - Kanashima, Takeshi
AU - Nakashima, Hiroshi
AU - Hamaya, Kohei
N1 - Publisher Copyright:
© 2016 The Japan Society of Applied Physics.
PY - 2016/6
Y1 - 2016/6
N2 - A possible low-temperature fabrication process of a gate-stack for Ge-based spin metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. First, since we use epitaxial ferromagnetic Heusler alloys on top of the phosphorous doped Ge epilayer as spin injector and detector, we need a dry etching process to form Heusler-alloy/n+-Ge Schottky-tunnel contacts. Next, to remove the Ge epilayers damaged by the dry etching process, the fabricated structures are dipped in a 0.03% diluted H2O2 solution. Finally, Al/SiO2/GeO2/Ge gate-stack structures are fabricated at 300 °C as a top gate-stack structure. As a result, the currents in the Ge-MOSFET fabricated here can be modulated by applying gate voltages even by using the low-temperature formed gate-stack structures. This low-temperature fabrication process can be utilized for operating Ge spin MOSFETs with a top gate electrode.
AB - A possible low-temperature fabrication process of a gate-stack for Ge-based spin metal-oxide-semiconductor field-effect transistor (MOSFET) is investigated. First, since we use epitaxial ferromagnetic Heusler alloys on top of the phosphorous doped Ge epilayer as spin injector and detector, we need a dry etching process to form Heusler-alloy/n+-Ge Schottky-tunnel contacts. Next, to remove the Ge epilayers damaged by the dry etching process, the fabricated structures are dipped in a 0.03% diluted H2O2 solution. Finally, Al/SiO2/GeO2/Ge gate-stack structures are fabricated at 300 °C as a top gate-stack structure. As a result, the currents in the Ge-MOSFET fabricated here can be modulated by applying gate voltages even by using the low-temperature formed gate-stack structures. This low-temperature fabrication process can be utilized for operating Ge spin MOSFETs with a top gate electrode.
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U2 - 10.7567/JJAP.55.063001
DO - 10.7567/JJAP.55.063001
M3 - Article
AN - SCOPUS:84973454873
SN - 0021-4922
VL - 55
JO - Japanese journal of applied physics
JF - Japanese journal of applied physics
IS - 6
M1 - 63001
ER -