TY - GEN
T1 - A low-power implementation of arctangent function for communication applications using FPGA
AU - Saber, M.
AU - Jitsumatsu, Yutaka
AU - Kohda, T.
PY - 2009/12/1
Y1 - 2009/12/1
N2 - A low power architecture to compute arctangent function which is suitable for broad-band communication applications is presented. This architecture aims to avoid high power consumption and long latency which are the main disadvantages to other methods based on CORDIC algorithm or conventional LUT methods or polynomial approximation. The architecture is implemented using FPGA, computes arctangent function with 3 clock pulses, and it is power dissipation is lower than Cordic algorithm by 80%.
AB - A low power architecture to compute arctangent function which is suitable for broad-band communication applications is presented. This architecture aims to avoid high power consumption and long latency which are the main disadvantages to other methods based on CORDIC algorithm or conventional LUT methods or polynomial approximation. The architecture is implemented using FPGA, computes arctangent function with 3 clock pulses, and it is power dissipation is lower than Cordic algorithm by 80%.
UR - http://www.scopus.com/inward/record.url?scp=74549167144&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=74549167144&partnerID=8YFLogxK
U2 - 10.1109/IWSDA.2009.5346438
DO - 10.1109/IWSDA.2009.5346438
M3 - Conference contribution
AN - SCOPUS:74549167144
SN - 9781424443802
T3 - Proceedings of the 4th International Workshop on Signal Design and Its Applications in Communications, IWSDA'09
SP - 60
EP - 63
BT - Proceedings of the 4th International Workshop on Signal Design and Its Applications in Communications, IWSDA'09
T2 - 4th International Workshop on Signal Design and Its Applications in Communications, IWSDA'09
Y2 - 19 October 2009 through 23 October 2009
ER -