A Hardware Maze Router with Application to Interactive Rip-Up and Reroute

Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki

Research output: Contribution to journalArticlepeer-review

15 Citations (Scopus)


This paper presents a new parallel-processing architecture for hardware routers based on the Lee algorithm. Unlike the existing machines, which require N2 processors to implement the Lee algorithm on an N x N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 × 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. Further, it is reported that the parallel-processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

Original languageEnglish
Pages (from-to)466-476
Number of pages11
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number4
Publication statusPublished - Oct 1986
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


Dive into the research topics of 'A Hardware Maze Router with Application to Interactive Rip-Up and Reroute'. Together they form a unique fingerprint.

Cite this