A flexible hardware barrier mechanism for many-core processors

Takeshi Soga; Hiroshi Sasaki; Tomoya Hirao; Masaaki Kondo; Koji Inoue

doi:10.1109/ASPDAC.2015.7058982

A flexible hardware barrier mechanism for many-core processors

Takeshi Soga, Hiroshi Sasaki, Tomoya Hirao, Masaaki Kondo, Koji Inoue

Department of I&E Visionaries

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

This paper proposes a new hardware barrier mechanism which offers the flexibility to select which cores should join the synchronization, allowing for executing multiple multi-threaded applications by dividing a many-core processor into several groups. Experimental results based on an RTL simulation show that our hardware barrier achieves a 66-fold reduction in latency over typical software based implementations, with a hardware overhead of the processor of only 1.8%. Additionally, we demonstrate that the proposed mechanism is sufficiently flexible to cover a variety of core groups with minimal hardware overhead.

Original language	English
Title of host publication	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	61-68
Number of pages	8
ISBN (Electronic)	9781479977925
DOIs	https://doi.org/10.1109/ASPDAC.2015.7058982
Publication status	Published - Mar 11 2015
Event	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 - Chiba, Japan Duration: Jan 19 2015 → Jan 22 2015

Publication series

Name	20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015

Other

Other	2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Country/Territory	Japan
City	Chiba
Period	1/19/15 → 1/22/15

All Science Journal Classification (ASJC) codes

Computer Science Applications
Electrical and Electronic Engineering
Control and Systems Engineering
Modelling and Simulation

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10.1109/ASPDAC.2015.7058982

Cite this

Soga, T., Sasaki, H., Hirao, T., Kondo, M., & Inoue, K. (2015). A flexible hardware barrier mechanism for many-core processors. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 (pp. 61-68). Article 7058982 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2015.7058982

A flexible hardware barrier mechanism for many-core processors. / Soga, Takeshi; Sasaki, Hiroshi; Hirao, Tomoya et al.
20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 61-68 7058982 (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Soga, T, Sasaki, H, Hirao, T, Kondo, M & Inoue, K 2015, A flexible hardware barrier mechanism for many-core processors. in 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015., 7058982, 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 61-68, 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015, Chiba, Japan, 1/19/15. https://doi.org/10.1109/ASPDAC.2015.7058982

Soga T, Sasaki H, Hirao T, Kondo M, Inoue K. A flexible hardware barrier mechanism for many-core processors. In 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. 61-68. 7058982. (20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015). doi: 10.1109/ASPDAC.2015.7058982

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A flexible hardware barrier mechanism for many-core processors

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