This paper describes a fast test pattern generator for large combinational circuit refining existing algorithms, the system can detect testable faults and identify redundant faults more effectively and mor efficiently. Three major contributions are presented in the paper, which are a fast growing algorithm finding path controllers, circuit narrowing technique and global implication based on equivalence. These modifications are described in detail and experimental results using ISCAS benchmark circuits are shown.
|Number of pages||7|
|Journal||Fujitsu Scientific and Technical Journal|
|Publication status||Published - Sept 1993|
All Science Journal Classification (ASJC) codes
- Human-Computer Interaction
- Electrical and Electronic Engineering
- Hardware and Architecture