TY - JOUR
T1 - A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits
AU - Mehdipour, Farhad
AU - Honda, Hiroaki
AU - Inoue, Koji
AU - Kataoka, Hiroshi
AU - Murakami, Kazuaki
N1 - Funding Information:
This research was supported in part by Core Research for Evolutional Science and Technology (CREST) of Japan Science and Technology Corporation (JST).
PY - 2011/1
Y1 - 2011/1
N2 - A large-scale reconfigurable data-path processor (LSRDP) implemented by single-flux quantum (SFQ) circuits is introduced which is integrated to a general purpose processor to accelerate data flow graphs (DFGs) extracted from scientific applications. A number of applications are discovered and analyzed throughout the LSRDP design procedure. Various design steps and particularly the DFG mapping process are discussed and our techniques for optimizing the area of accelerator will be presented as well. Different design alternatives are examined through exploring the LSRDP design space and an appropriate architecture is determined for the accelerator. Primary experiments demonstrate capability of the designed architecture to achieve performance values up to 210 Gflops for attempted applications.
AB - A large-scale reconfigurable data-path processor (LSRDP) implemented by single-flux quantum (SFQ) circuits is introduced which is integrated to a general purpose processor to accelerate data flow graphs (DFGs) extracted from scientific applications. A number of applications are discovered and analyzed throughout the LSRDP design procedure. Various design steps and particularly the DFG mapping process are discussed and our techniques for optimizing the area of accelerator will be presented as well. Different design alternatives are examined through exploring the LSRDP design space and an appropriate architecture is determined for the accelerator. Primary experiments demonstrate capability of the designed architecture to achieve performance values up to 210 Gflops for attempted applications.
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U2 - 10.1016/j.sysarc.2010.07.009
DO - 10.1016/j.sysarc.2010.07.009
M3 - Article
AN - SCOPUS:78650283449
SN - 1383-7621
VL - 57
SP - 169
EP - 179
JO - Journal of Systems Architecture
JF - Journal of Systems Architecture
IS - 1
ER -