A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor

Farhad Mehdipour; Hamid Noori; Bahman Javadi; Hiroaki Honda; Koji Inoue; Kazuaki Murakami

doi:10.1109/ASPDAC.2009.4796540

A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor

Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki Murakami

Department of I&E Visionaries

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Citations (Scopus)

Abstract

Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO ) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.

Original language	English
Title of host publication	Proceedings of the ASP-DAC 2009
Subtitle of host publication	Asia and South Pacific Design Automation Conference 2009
Pages	564-569
Number of pages	6
DOIs	https://doi.org/10.1109/ASPDAC.2009.4796540
Publication status	Published - 2009
Event	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 - Yokohama, Japan Duration: Jan 19 2009 → Jan 22 2009

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other	Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
Country/Territory	Japan
City	Yokohama
Period	1/19/09 → 1/22/09

All Science Journal Classification (ASJC) codes

Computer Science Applications
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Access to Document

10.1109/ASPDAC.2009.4796540

Cite this

Mehdipour, F., Noori, H., Javadi, B., Honda, H., Inoue, K., & Murakami, K. (2009). A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. In Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009 (pp. 564-569). Article 4796540 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2009.4796540

A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. / Mehdipour, Farhad; Noori, Hamid; Javadi, Bahman et al.
Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. 2009. p. 564-569 4796540 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Mehdipour, F, Noori, H, Javadi, B, Honda, H, Inoue, K & Murakami, K 2009, A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. in Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009., 4796540, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 564-569, Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009, Yokohama, Japan, 1/19/09. https://doi.org/10.1109/ASPDAC.2009.4796540

Mehdipour F, Noori H, Javadi B, Honda H, Inoue K, Murakami K. A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. In Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. 2009. p. 564-569. 4796540. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1109/ASPDAC.2009.4796540

Mehdipour, Farhad ; Noori, Hamid ; Javadi, Bahman et al. / A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. Proceedings of the ASP-DAC 2009: Asia and South Pacific Design Automation Conference 2009. 2009. pp. 564-569 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).

@inproceedings{2b22d513a04a4d9890347b1c50587c6e,

title = "A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor",

abstract = "Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO ) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.",

author = "Farhad Mehdipour and Hamid Noori and Bahman Javadi and Hiroaki Honda and Koji Inoue and Kazuaki Murakami",

year = "2009",

doi = "10.1109/ASPDAC.2009.4796540",

language = "English",

isbn = "9781424427482",

series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

pages = "564--569",

booktitle = "Proceedings of the ASP-DAC 2009",

note = "Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009 ; Conference date: 19-01-2009 Through 22-01-2009",

}

TY - GEN

T1 - A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor

AU - Mehdipour, Farhad

AU - Noori, Hamid

AU - Javadi, Bahman

AU - Honda, Hiroaki

AU - Inoue, Koji

AU - Murakami, Kazuaki

PY - 2009

Y1 - 2009

N2 - Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO ) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.

AB - Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consuming and need a considerable design effort. A combined analytical and simulation-based model (CAnSO ) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.

UR - http://www.scopus.com/inward/record.url?scp=64549154845&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=64549154845&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2009.4796540

DO - 10.1109/ASPDAC.2009.4796540

M3 - Conference contribution

AN - SCOPUS:64549154845

SN - 9781424427482

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 564

EP - 569

BT - Proceedings of the ASP-DAC 2009

T2 - Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009

Y2 - 19 January 2009 through 22 January 2009

ER -

A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor

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