TY - GEN
T1 - A character size optimization technique for throughput enhancement of character projection lithography
AU - Sugihara, Makoto
AU - Takata, Taiga
AU - Nakamura, Kenta
AU - Inanami, Ryoichi
AU - Hayashi, Hiroaki
AU - Kishimoto, Katsumi
AU - Hasebe, Tetsuya
AU - Kawano, Yukihiro
AU - Matsunaga, Yusuke
AU - Murakam, Kazuaki
AU - Okumura, Katsuya
PY - 2006
Y1 - 2006
N2 - We propose a character size optimization technique to enhance the throughput of maskless lithography as well as photomask manufacture. The number of electron beam shots to draw the patterns of circuits is a dominant factor in the manufacture time and the cost for devices. Our technique is capable of drastically reducing them by optimizing the size of characters, which are the patterns to project and are placed on CP masks. Experimental results show that our technique reduced 72.0% of EB shots in the best case, comparing with the ad hoc character sizing.
AB - We propose a character size optimization technique to enhance the throughput of maskless lithography as well as photomask manufacture. The number of electron beam shots to draw the patterns of circuits is a dominant factor in the manufacture time and the cost for devices. Our technique is capable of drastically reducing them by optimizing the size of characters, which are the patterns to project and are placed on CP masks. Experimental results show that our technique reduced 72.0% of EB shots in the best case, comparing with the ad hoc character sizing.
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M3 - Conference contribution
AN - SCOPUS:33745605667
SN - 0780393902
SN - 9780780393905
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 2561
EP - 2564
BT - ISCAS 2006
T2 - ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems
Y2 - 21 May 2006 through 24 May 2006
ER -