A 3.0-5.0 GHz high linearity and low power CMOS up-conversion mixer for UWB applications

S. A.Z. Murad; R. K. Pokharel; H. Kanaya; K. Yoshida

doi:10.1109/EDSSC.2010.5713741

A 3.0-5.0 GHz high linearity and low power CMOS up-conversion mixer for UWB applications

S. A.Z. Murad, R. K. Pokharel, H. Kanaya, K. Yoshida

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

9 Citations (Scopus)

Abstract

This paper presents a high linearity and low power up-conversion mixer at 3.0-5.0 GHz for UWB applications in TSMC 0.18-μm CMOS technology. The design based on Gilbert-cell active double-balanced mixer using a capacitor located in parallel with the intrinsic gate-source capacitor of a transconductance stage for high linearity. The source degeneration inductors helps to improve linearity and IF input matching. The current injection is employed to increase gain and obtained low power. The up-conversion mixer converts an input of 100 MHz intermediate frequency (IF) signal to an output of 3.0-5.0 GHz radio frequency (RF) signal. The post-layout simulation results indicated that the proposed mixer achieves a higher input third order intercept point (IIP3) of 13.5-dBm, convention gain of 2.3-dB and low power of 7.1-mW at 1.2-V power supply.

Original language	English
Title of host publication	2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010
Publisher	IEEE Computer Society
ISBN (Print)	9781424499977
DOIs	https://doi.org/10.1109/EDSSC.2010.5713741
Publication status	Published - Jan 1 2010

Publication series

Name	2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/EDSSC.2010.5713741

Cite this

Murad, S. A. Z., Pokharel, R. K., Kanaya, H., & Yoshida, K. (2010). A 3.0-5.0 GHz high linearity and low power CMOS up-conversion mixer for UWB applications. In 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010 Article 5713741 (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010). IEEE Computer Society. https://doi.org/10.1109/EDSSC.2010.5713741

A 3.0-5.0 GHz high linearity and low power CMOS up-conversion mixer for UWB applications. / Murad, S. A.Z.; Pokharel, R. K.; Kanaya, H. et al.
2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010. IEEE Computer Society, 2010. 5713741 (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Murad, SAZ, Pokharel, RK , Kanaya, H & Yoshida, K 2010, A 3.0-5.0 GHz high linearity and low power CMOS up-conversion mixer for UWB applications. in 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010., 5713741, 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010, IEEE Computer Society. https://doi.org/10.1109/EDSSC.2010.5713741

Murad SAZ, Pokharel RK , Kanaya H, Yoshida K. A 3.0-5.0 GHz high linearity and low power CMOS up-conversion mixer for UWB applications. In 2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010. IEEE Computer Society. 2010. 5713741. (2010 IEEE International Conference of Electron Devices and Solid-State Circuits, EDSSC 2010). doi: 10.1109/EDSSC.2010.5713741

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AB - This paper presents a high linearity and low power up-conversion mixer at 3.0-5.0 GHz for UWB applications in TSMC 0.18-μm CMOS technology. The design based on Gilbert-cell active double-balanced mixer using a capacitor located in parallel with the intrinsic gate-source capacitor of a transconductance stage for high linearity. The source degeneration inductors helps to improve linearity and IF input matching. The current injection is employed to increase gain and obtained low power. The up-conversion mixer converts an input of 100 MHz intermediate frequency (IF) signal to an output of 3.0-5.0 GHz radio frequency (RF) signal. The post-layout simulation results indicated that the proposed mixer achieves a higher input third order intercept point (IIP3) of 13.5-dBm, convention gain of 2.3-dB and low power of 7.1-mW at 1.2-V power supply.

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A 3.0-5.0 GHz high linearity and low power CMOS up-conversion mixer for UWB applications

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