29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic

Ikki Nagaoka; Masamitsu Tanaka; Koji Inoue; Akira Fujimaki

doi:10.1109/ISSCC.2019.8662351

29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic

Ikki Nagaoka, Masamitsu Tanaka, Koji Inoue, Akira Fujimaki

Department of I&E Visionaries

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

33 Citations (Scopus)

Abstract

A multiplier based on superconductor single-flux-quantum (SFQ) logic is demonstrated up to 48GHz with the measured power consumption of 5.6 mW. The multiplier performs 8 × 8 - bit signed multiplication every clock cycle. The design is based on a bit-parallel, gate-level-pipelined structure that exploits ultimately high-throughput performance of SFQ logic. The test chip fabricated using a 1.0- μ {m}, 9-layer process consists of 20,251 Nb/AlOx/Nb Josephson junctions (JJs). The correctness of operation is verified by on-chip high-speed testing.

Original language	English
Title of host publication	2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	460-462
Number of pages	3
ISBN (Electronic)	9781538685310
DOIs	https://doi.org/10.1109/ISSCC.2019.8662351
Publication status	Published - Mar 6 2019
Event	2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 - San Francisco, United States Duration: Feb 17 2019 → Feb 21 2019

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume	2019-February
ISSN (Print)	0193-6530

Conference

Conference	2019 IEEE International Solid-State Circuits Conference, ISSCC 2019
Country/Territory	United States
City	San Francisco
Period	2/17/19 → 2/21/19

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2019.8662351

Cite this

Nagaoka, I., Tanaka, M., Inoue, K., & Fujimaki, A. (2019). 29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic. In 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019 (pp. 460-462). Article 8662351 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2019-February). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2019.8662351

29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic. / Nagaoka, Ikki; Tanaka, Masamitsu; Inoue, Koji et al.
2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 460-462 8662351 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 2019-February).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nagaoka, I, Tanaka, M, Inoue, K & Fujimaki, A 2019, 29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic. in 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019., 8662351, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, vol. 2019-February, Institute of Electrical and Electronics Engineers Inc., pp. 460-462, 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019, San Francisco, United States, 2/17/19. https://doi.org/10.1109/ISSCC.2019.8662351

Nagaoka I, Tanaka M, Inoue K, Fujimaki A. 29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic. In 2019 IEEE International Solid-State Circuits Conference, ISSCC 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 460-462. 8662351. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2019.8662351

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abstract = "A multiplier based on superconductor single-flux-quantum (SFQ) logic is demonstrated up to 48GHz with the measured power consumption of 5.6 mW. The multiplier performs 8 × 8 - bit signed multiplication every clock cycle. The design is based on a bit-parallel, gate-level-pipelined structure that exploits ultimately high-throughput performance of SFQ logic. The test chip fabricated using a 1.0- μ {m}, 9-layer process consists of 20,251 Nb/AlOx/Nb Josephson junctions (JJs). The correctness of operation is verified by on-chip high-speed testing.",

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29.3 A 48GHz 5.6mW Gate-Level-Pipelined Multiplier Using Single-Flux Quantum Logic

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